This invention relates to high frequency semiconductor devices, and more particularly to a field effect transistor with a vertical structure for high power, high frequency applications.
Conventional field effect transistors are planar devices with the source, gate and drain electrodes on the same surface of the semiconductor and the current flow substantially along the surface. The most advanced field effect transistor for high power, high efficiency applications is a planar device fabricated on a gallium arsenide layer of n-type conductivity that has been epitaxially grown on a semi-insulating gallium arsenide substrate (see FIG. 1). The source and drain electrodes are metals ohmically attached to the gallium arsenide layer, which may be locally doped or defined by mesa etching to facilitate the ohmicity of the contact, and the gate electrode is a metal which forms a Schottky blocking contact to the gallium arsenide layer. Fabrication problems exist in delineating with sufficient resolution the source-gate and gate-drain spacing. For high frequency applications the gate-drain spacing is of the order of one micron or less in order to take advantage of a higher saturation velocity of the electron in gallium arsenide before the intervalley transfer mechanism sets in. Such a small dimension requires the utmost in lithographic resolution in the device fabrication. Other factors limiting the efficient utilization of the field effect transistor at high or microwave frequencies include the parasitic series resistance in the source and drain, the resistance of the gate metal, and various inductances such as the inductance of the grounding leads for the source. For high power application, the gate metal "line" acts as a lossy transmission line, thus limiting the useful size of the device.
The semi-insulating substrate presents several problems. Heat sinking is not divorced from circuit considerations due to the presence of a thick semi-insulating substrate. Such a substrate normally contains a large concentration of various impurities, but the activated carriers are so compensated as to have little electrical conductivity. The deep impurity levels may act as traps and become charged, thus affecting the performance of the active layer. It is also believed that the radiation damage affecting field effect transistor performance is a manifestation of the charged states in the semi-insulating substrate.
The VMOS (vertical metal-oxide-semiconductor) transistor with a V groove configuration is essentially a planar or single surface device on the folded surfaces of the groove.
The objects of the present invention are to improve the performance of the field effect transistor and achieve a higher power level and higher frequency by means of a novel configuration which allows minimization of the parasitics, has improved circuit simplicity and heat sinking, makes better utilization of the semiconductor area within the maximum dimensions determined by the wavelength, and avoids the need for a semi-insulating substrate.